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Pr.1 PROGRAMMING METHOD sinusoidal signals sum of two angles.
Purpose: to get acquainted with the various algorithms of formation of sinusoidal signals, the development and debugging of the generator of sinusoidal signals based on recursively-analytical method the sum of two angles to the processor TMS320VC5510 (laboratory model) TMS320VC5510 DSP Starter Kit (DSK).
THEORETICAL BACKGROUND
Formula sum of two angles.
There are several analytical (computational) methods for the formation of sinusoidal signals. One such method is based on formulas of the sum of two angles:
This method is applicable for serial sampling a sine wave generation, and allows you to calculate the next count functions such as sin (an) = sin (a (n-1) + a), a previous sin (a (n-1)).
Using a(n-1) as α and β as a and denoting S1 = sin (a), C1 = cos (a), Sn (n) = sin (an), Cn (n) = cos (an) obtain the following expressions for calculating the next value of sine and cosine:
Initial data for calculating the first harmonic (with the lowest possible frequency) are the following values: Sn (0) = 0, Cn (0) = 1 – sine and cosine values for zero arguments; N – length of sample (number of counts in the first harmonic); a = 2Π / N, – the minimum increment of the argument and S1 = sin (2Π / N), C1 = cos (2Π / N) – values of sine and cosine for the minimum of the argument.
Figure 1.1 shows an example of a sinewave with a period of 8 samples (N = 8).
Given that the initial values for the k-th harmonic are the initial angle β = ak, Sk = sin (ak) and Ck = cos (ak), for their calculation can use the same formula:
Initial data for calculation, as in the expression (1.2) are the values of Sk (0) = 0 and Ck (0) = 1
Putting the data in memory as follows Cn, Sn, Ck, Sk, C1, S1, you can use the same routine with the indirect addressing for the calculation of both the regular readings of harmonic Sn and Cn, and the initial values of Sk and Ck.
What initially set the pointer (the address in the auxiliary register) on Ck and calculate the next value Ck and Sk, and then on Cn and calculate the required number of readings regular harmonic Sn and Cn:
Notes for achieving a programming task:
When programming sinusoid this method should take into account the following observations:
• using two auxiliary register and two operand commands (Xmem, Ymem), the calculation of sine (cosine) can be performed by three operand commands;
• Since the assembler TMS320VC5510 has no guidelines to specify the fractional numbers, decimal numbers (format Q15) are translated into integers by multiplying by 32768, and is used directive .word;
• Since there is no code for the positive value of 1.0, then for the job cos (0) used an approximate value 7FFFh = 1-2-15.
• to formed sinusoid (cosine) are not damped, the initial value of C1 = cos (2Π / N) increases by one or two units of LSB, and calculations are performed in the highest part of the battery during a correction mode overflow.
Algorithm for generating the sequence of sinusoids.
For follow-up study of digital filters is required to build a generator sequence of sine waves with increasing frequency.
Scheme algorithm for generating a sequence of sine waves with increasing frequency is shown in Fig. 3.2.
Figure 3.2. Scheme algorithm for generating a sequence of sinusoids
The task for laboratory work
Implement the algorithm for forming a sequence of sine (cosine) with the following parameters:
Number Of Variant Tasks
9 sinusoid with a period of 100 … 1500 Hz in increments of 150 Hz and sample length N = 8.
DELIVERABLES for pr.1:
1. Explore the theoretical knowledge on laboratory work.
2. According to the assignment to write the program and execute.
3. Support documentation: user manual on how to run the program, show the results of compilation and the analyze of the results and how they prove the theory explained above.
4. Write a report. (REPORT CONTENTS : 1. Purpose of the work. 2. Description of the algorithm of the program. 3. Program listing with comments. 4. Conclusions of the work).
Pr.2 Working with PDP controller. Modify the given program main_dma1.c (comes with dma1.cmd, dma1.pjt, vectors_dma1.s55) for the program to make a transfer of a single frame of 32 items by 4 bits in each of 4-th PDP channel with interrupt transmission since the beginning of the last frame. Record transmitted data in the memory section SARAM10.
http://en.wikipedia.org/wiki/Pdp-11
Theoretical information.
PDP Data Types: Byte, Element, Frame, Block.
DMA direct memory access can work with data on four levels:
1) Byte – 8 bit value. Bandwidth – the smallest unit of data transmitted in the channel of direct access to memory.
2) Element – one or more bytes, depending on the type of programmable data element – an 8-bit, 16-bit or 32-bit value. The transfer element can not be interrupted: all of its bytes are transferred to the port before another channel or HPI can take the port under its control.
3) frame – one or more elements. Transmission frame may be interrupted by transfers between items.
4) Unit – one or more frames. Each channel can transmit one block of data (once or more times). Block approach is forwarding can be interrupted transfers between the frames and the transfer of elements.
For each of the 6 channel direct memory access, you can determine the number of frames in a block (register DMACFN), the number of elements in a frame (register DMACEN), and the number of bytes in the element (using the DATATYPE bits in the register DMACSDP).
Set start addresses in the channel
During the data transmission channel direct memory access, initial address from which data is read, is called the source address read, the initial address to which data is recorded – starting address of record. This – the address byte. From the perspective of the PDP controller, each 8 bits of memory space or input – output has its own address. Each channel contains the following registers in order to determine the source address:
Destination register
DMACSSAL source address that was read (youngest part)
DMACSSAU source address that was read (the older part)
DMACDSAL source address of record (youngest part)
DMACDSAU source address of record (the oldest part)
Source address in memory
The memory card is available PDP controller
The map shows the address word (23-bit addresses) used by the CPA and the address byte (24-bit addresses) used by the PDP controller. To load the registers the source address of the read / write must:
1) Determine the correct starting address: check for any restrictions on data types, see the description for the DATATYPE bits register DMACSDP. If we define the word address, shifts it left by 1 bit to form a byte address with 24 bits. For example, the address of the word – 02 4000h, must be converted to a byte address 04 8000h.
2) Download the 16 least significant bits (LSB) byte address to register DMACSSAL (for reading) or to register DMACDSAL (for writing).
3) Download the 8 most significant bits (MSB) byte address of 8 bits register junior DMACSSAU (for reading) or DMACDSAU (for writing).
Note:
Address 00 0000h – 00 005Fh (which correspond to byte address 00 0000h – 00 00BFh), are reserved for the registers to memory mapped (MMRs) CPU and can not be used.
Starting address in the space of input – output
Site space input – output available to the PDP controller
The map shows the address of the word (16-bit addresses) used by the CPA and the address byte (17-bit addresses) used by the PDP controller. To load the registers in the source address of the read / write must:
1) Determine the correct source address: check any restrictions on data types (see the description for the DATATYPE bits register DMACSDP). If we define the word address, shifts it left by 1 bit to form a byte address with 17 bits. For example, the word address – 8000h must be converted to 1 byte address 0000h.
2) Download the 16 least significant bits (LSB) byte address to register DMACSSAL (for reading) or to register DMACDSAL (for writing).
3) Download 1 most significant bit (MSB) byte address least significant bit of register DMACSSAU (for reading) or DMACDSAU (for writing).
Control of channel activity
PDP controller can send an interrupt to the CPU in response to operational events listed in Table 1.
Table 1. Operating Events PDP controller and associated bits and interrupts
Operational Events Bit allowing interrupt Status bit Interrupts
Transmition of unit finished BLOCKIE
BLOCK
Interrupt Channel
Transfer of the last frame started LASTIE
LAST
Interrupt Channel
Transmission frame completed FRAMEIE
FRAME
Interrupt Channel
The first half of the current frame is finished* HALFIE
HALF
Interrupt Channel
Event synchronization missed DROPIE
DROP
Interrupt Channel
An error has occurred because of the timeout TIMEOUTIE
TIMEOUT
Terminating bus error
* – For the frame with an odd number of elements, the phenomenon of half of the frame is as soon as the number of transferred elements, than the number remaining.
Each channel has a bit interrupt enable (IE) in the interrupt control register (DMACICR) and some relevant bits of the register states (DMACSR). If one of the events in the operating table is, DMA checks the (notes) corresponding bit IE and acts accordingly as follows:
• If bit IE = 1 (interrupt enabled), the DMA sets the appropriate status bit and sends a corresponding interrupt request to the CPU. Register DMACSR automatically cleared if your program reads the register.
• If bit IE = 0, no interrupt is sent, and status bit is not working.
Register DMACSR also has a bit synchronization (SINC), which is used to choose the event synchronization for the channel. This bit indicates when the selected synchronization phenomenon occurred (SINC = 1) and when it is-served (SINC = 0).
Interrupt Channel
Each of the 6 channel has its own interrupt. As shown in Figure 1, an interrupt channel is constructed under the scheme of the logical OR of all enabled operating events, except the phenomenon of lock time (the phenomenon of lock time generates an interrupt request bus error). You can choose any combination of these five events, setting or clearing the corresponding bit IE in the interrupt control register (DMACICR) for the channel. You can determine what phenomenon (phenomena) caused an interrupt, reading the bits in the status register (DMACSR) for the channel. Bits DMACSR not automatically cleared. Reading DMACSR clears all bits of state. DMACSR should be read each time the interrupt occurs to clear the status bits, waiting to be processed.
Figure 1. Call the interrupt request of the Canal
Example interrupt. For example, you control the action on channel 1 and the state of bits in DMACICR the following:
BLOCKIE = 0
LASTIE = 0
FRAMEIE = 1
HALFIE = 0
DROPIE = 1
When the current transmission frame is executed or the phenomenon of synchronization is missing, will be sent to an interrupt request channel 1. To define one or both events started interruption, you can take bits and DROP FRAME in the register DMACSR.
Interrupt channel 1 sets the corresponding bit flag in the register flag is a CPU, a CPU can respond or ignore the interrupt.
DELIVARABLES for pr.2:
1. Modified Code
Modify the proposed program under the following conditions PDP data:
№ Number of variant
9 Transfer of a single frame of 32 items by 4 bits in each of 4-th PDP channel with interrupt transmission since the beginning of the last frame. Record transmitted data in the memory section SARAM10.
2. User manual how to execute the program.
3. Sample output with recorded data and it’s analyzed.
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