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Solve a bug on Verilog NetFPGA implementation by gibanezfer

Posted by | December 24, 2012 | Newest Projects

We need a Verilog expert to solve a bug on NetFPGA implementation of a modified Ethernet switch. It might be related with timing limitations of the Verilog code to gate conversion handling table writing and reading of MAC addresses at a table… (Budget: €18-€36 EUR, Jobs: Electronics, Verilog / VHDL)

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